1. Field of the Invention
This invention relates to design verification of integrated circuits, and more specifically, to the scheduling of specific test events.
2. Description of the Related Art
A common method of designing integrated circuits involves the use of a hardware description language, or HDL. Once an initial design is completed, simulations may be run to verify the behavior of the circuit. If the circuit does not meet behavioral specifications, the design may be modified to allow the circuit to perform its desired function. The ability to verify a design at a simulation level prior to constructing working hardware models may allow for significant cost savings in the overall design process.
In order to test a circuit during the design phase, many designers use a virtual test bench. A virtual test bench is a software package that allows a user to construct a virtual environment in which the simulation will take place. This virtual environment may include input stimuli and models of external devices, as well as a model of the device under test (DUT). In some cases, the virtual test bench is a component of the hardware description language used to design the circuit, while a separate software package is used to effect the simulation. For example, the hardware description language Verilog may use a software package known as Verilog-XL. The Verilog-XL package is used to simulate the virtual test bench environment specified by the Verilog hardware description language.
For a given simulation, a user may describe a specific set of events which are to occur. These events will employ the various resources of the DUT in order to verify their function. Such resources may include input/output ports, FIFO (first-in first out) memories, registers, drivers, and other functional units/circuitry. Typically, the scheduling of the specified events occurs dynamically during the actual simulation. One hazard of using dynamic scheduling is the possibility of resource conflicts. Such resource conflicts may be prevented by the use of semaphores. A semaphore will lock the resource in use, preventing its use by other resources at a given time, as well as preventing the simulation from attempting to use the resource for multiple events simultaneously.
Although semaphores may simplify the dynamic scheduling of events in a simulation, there may be overhead associated with their use. Using a semaphore to lock a resource during a given test may not allow the full functionality of the given resource to be properly tested. For example, a typical FIFO memory may be read from and written to simultaneously, even when the FIFO is full. However, when the simulated FIFO is locked by a semaphore, simultaneous FIFO reading and writing may be blocked. This can result in an incomplete test of the FIFO memory. As an alternative, the simulation may be accomplished without the use of semaphores, but this may lead to resource conflicts that may potentially result in the performance of illegal operations.
Because of the limitations of dynamic scheduling, it is possible that some complex test scenarios will not be simulated during a given test. In order to verify the full functionality of a given resource, multiple simulations may need to be performed. In some cases, it may be impossible, even with multiple simulations, to verify the full functionality of a resource using dynamic scheduling.